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Multilayer Boards (MLBs) By definition, MLBs have three or more circuit layers (see Fig 54) Main applications of MLBs used to be confined to sophisticated industrial electronic products Now, however, they are the mainstream of all electronic devices, including consumer products such as portable video cameras, cellular phones, and audio discs 5623 Layer Count As personal computers and workstations become more powerful, mainframe computers and supercomputers are being replaced in many applications by these smaller machines As a result, the use of highly sophisticated MLBs, which have layer counts over 70, are being reduced, but the technology to produce them is proven At the other end of the layer-count spectrum, thin and high-density MLBs with layer counts between 4 and 8 are mainstream.

Industry standard package CMOS/TTL output 3.3-V operation available Large fanout capability More details are available at this manufacturer s Web site: www.ndk.com/products/guide.htm Figure 5.4 illustrates an 8-pin crystal clock and pinout.

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The drive toward thinner MLBs will continue and is made possible by the continuing concurrent advancement of materials and equipment to handle thin core materials 5624 Via and Via Production Technologies As PWBs have had to address the issues of higher speed, higher density, and the rise of surface-mount components that use both sides, the need to communicate between layers has increased dramatically At the same time, the space available for vias has decreased, causing a continuing trend toward smaller holes, more holes on the board, and the decline of the use of holes that penetrate the entire board, which use space on all layers As a result, the use of buried and blind vias has become a standard part of multilayer board technology, driven by the need for this increased package density (Fig 54).

One of the immediate issues that arise from these trends is the problems of drilling and the associated cost of this fabrication step Printed wiring boards, which once were stacked three high on a drilling machine, must be drilled individually, and the number of holes per board has risen, to accommodate the need for vias This has caused a major problem for fabricators, who find that a lack of drilling capacity is creating a big demand on funds for additional machines, while the cost of drilling continues to increase dramatically Therefore, alternate methods for creating vias are being developed These pressures will be ongoing, and therefore the process listed here, or some equivalent, will undoubtedly become more important as the drive to miniaturization continues and drilling individual holes becomes less and less practical..

FIGURE 5.4 Cross-section multilayer board with buried via holes. Buried vias are built into each of the double-sided boards that make up the final multilayer structure.

Rolling Element, Hydrodynamic and Hydrostatic Bearings Volumetric flow, Q capillary and orifice inflow restrictor For design conditions, the volumetric flow for both capillary and orifice restrictors are similar: Ps Q = Ro (1 + ) 225 Q = 553 (1 + 1 ) Q = 0203 in3 s 1 330 10 6 m3 s 1 Pumping power, Pp capillary and orifice inflow restrictor Pp = QPs Pp = 0203 225 517 W Pp = 458 in lbf s 1 For the 10 pads, the total pumping power is multiplied by the number of pads: nPp = 458 10 nPp = 458 in lbf s 1 nPp 007 hp 517 W Friction force, FL and Friction Power, Pf rectangular pad

These processes have been developed to mass-produce vias without drills. Surface Laminar Circuits (SLCs). The most notable MLB technology developed to form vias is the sequential fabrication of multilayers without press operations. This is particularly important for surface blind via holes. The process for fabricating a board using surface laminar circuits is as follows (see Fig. 5.5): Innerlayer ground and power distribution patterns are formed. Panel receives an oxide treatment. Insulating photosensitive resin is coated over the panel by curtain or screen-coating methods. Holes are formed by photoexposure and development. Panel is metallized by usual copper reduction process (consisting of catalyzing and electroless copper plating or by direct metallization process). 6. Thicker deposition of copper is made by continuation of electroless copper plating or galvanic plating. 7. Circuit patterns are formed by dry film tenting process. 1. 2. 3. 4. 5.

FIGURE 5.5 Example of surface laminar circuit (SLC) board cross section. (Courtesy IBM Yasu and Ciba-Geigy Limited.)

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